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In this tutorial, I will cover the creation of an anti-aliased digital hard sync oscillator in...

In this tutorial, I will cover the creation of an anti-aliased digital hard sync oscillator in Reaktor. To achieve this, we will be using structures introduced in my previous tutorials on core oscillator design. You will also want to be familiar with aliasing, interpolation, and the BLIT technique for creating anti-aliased waveforms.


Hard synchronization is an analog synth technique that uses two oscillators termed the ‘master’ oscillator and the ‘slave’ oscillator. Whenever the master oscillator restarts it’s cycle, the slave oscillator is told to restart it’s cycle as well. Generally speaking the slave oscillator has a higher frequency than the master, meaning it will complete more than one cycle for each cycle completed by the master oscillator:

Today we will create a system that works for a slave oscillator frequency up to twice that of the master oscillator. The structure can also be extended to create more extreme differences if desired.

Hard sync is a very common effect in analog synthesizers, which I believe was originally intended to combat oscillator drift (many analog systems had problems with this, see here for more). Since hard sync is a a popular analog effect, it is only natural that synth designers working in the digital domain will want to emulate it.


There is a class of Primary oscillators in Reaktor that have a hard sync capability built in, the Sine Sync, Triangle Sync, etc.

Using these oscillators to create a hard sync is easy:

As you can see, the slave oscillator is used as an audio output (the master oscillator is really not that interesting, after all).

A setup like this will cause aliasing however. While the Primary oscillators do make an attempt at bandlimiting the signal, the aliasing is audible at the right settings. Instead, let’s build a simple system in Core to allow for hard sync.


In this section, I’ll begin to implement the ideas laid out in this paper, which outlines the creation of a bandlimited hard sync system.

One element that is relied heavily upon for this implementation is what is called a fractional delay line, which is really a type of filter that can give an approximation for the values of a digital waveform in-between the known points. For example, delaying a signal by 2 samples is easy – simply output the value that was at the input 2 samples ago. However, a fractional delay line can also give the value of the wave at 2.375 samples ago, something a normal delay line cannot do.

While there are several filter design types that can fit this description, we also need the delay time to be variable and not constant. The best method I have found is to use interpolation to determine the values between the known points. To this end, I created the following structure:

The ‘D’ input is the delay time. Using a modulo function, the integer value is stripped out and sent to the delay line, and the fractional value is used to find the coefficients for our interpolator. I won’t go too deep into the math of the interpolation as it is confusing and not our focus anyway. If the reader has interest, the paper I used to create this macro is here.

In any event, you may use any type of interpolation here, the more accurate it is, the less aliasing the hard sync effect will end up having. I find that using 4 points as I have here is a usually a good trade off between efficiency and performance.

Notice that the delay line outputs four values instead of it’s usual one. I made the following changes to the structure:

This gives us the four values to use for interpolation.

The whole structure then essentially acts as an FIR filter with an additional delay tacked on at the beginning.


Using this fractional delay, we want to implement this structure:

Which basically implements a comb filter on top of the sawtooth.

The value τ is the length of one period of the slave oscillator, in samples, and is used as the length of the fractional delay line outlined above. The value C is used as a scalar, I could not find a source for it’s value in the text. Through experimenting, I came up with the following structure:

The last thing we must do is add a DC trap to the end of the signal chain, since hard sync can cause DC to be added to the signal. I have a DC trap from a previous tutorial you can find here.

Download the oscillator here (DC Trap not included!).


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