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Reaktor core is very powerful, but can be a little daunting at first. In this post I’m going...

Reaktor core is very powerful, but can be a little daunting at first. In this post I’m going to build a counter. Nothing fancy, just nuts and bolts.

I was lucky enough to learn from Martijn Zwartjes while at CalArts, and I’m going to try my best to show some of the things were key to helping me understand Reaktor Core a little better.

Core Audio Cell

Audio vs. Event Core Cell

To start we need to create an empty “Audio core cell”. The reason we need an Audio cell instead of an Event cell, is that we need access to the Sample Rate Clock. Since the Sample clock only runs at Audio rate, it only works right in the Audio core cell. It is possible to select a Sample Rate Clock in an Event core cell, but it wont work the way we need.

Read, Write, and Add. All Driven by the Clock

Next we are going to add three objects. A read, a write and an add. The Read and Write objects have a special connection called an OBC. The OBC goes into the inlets without any dots. You will see these OBC connections on modules that deal with memory functions. There is more to the OBC connections, but we’ll deal with that later. For now, the Read module is hooked up to an Add, the sum is then fed into a Write module, which is then read by the Read module, which then adds the value with our constant, which is then fed into the Write module….. and so on and so on. As you can see we have created a nice little feedback loop.

Read Write and Add
Read Write and Add

The whole loop is driven by a clock source at the top left of the Read module. We are using the sample rate clock for this example, and in fact most counters I’ve built use this as the clock source. This means that 44100 times a second (or whatever your sample rate happens to be) the loop will add a 1 to the current value. As the loop currently stands, we will have a value of 44100 at the end of 1 second. That’s nice, but a counter that goes between 0 and 1 would be much more useful.

Setting our increment

Since we can’t change the rate of our clock source (we could, but there is a much nicer way to do this) we need to change the amount that we increment for each loop iteration. Instead of adding 1 every clock, we will add the sample rate’s reciprocal. In other words, we will add 1/44100 th every clock. This will give us a value of 1 at the end of one second.

Sample Rate Reciprocal
Sample Rate Reciprocal

Wrapping it up

However, our clock will now blow past 1 and keep counting at sample rate, incrementing a whole number every second. We want our counter to wrap and restart every time it reaches 1, so we need to implement a little comparison.

Wrap
Wrap

In the flow menu you will find a router object, and a compare. These two modules work together to provide some very useful routing control. In our counter, we want it to say that every time the input is larger than 1 we want to subtract the value from itself. This will give us a 0 and then restart the loop.

The Router module outputs the bottom if our compare statement is false, and outputs the top if our compare statement is true. The merge module takes the input from either the top or bottom and sends it out. If the merge receives simultaneous inputs, it only sends out the one at the lowest input.

Ins and Outs

Now a few last things. First, we need to get the values out of the core cell. It’s important that we pull the values from the right point, as the values are different at different points for each clock event. For this counter we will pull straight from the Read module. Secondly, it would be nice to control the speed of the counter from a knob. All we have to do is multiply the increment by some value between 0 and x and it will change the increment rate. The larger the value, the faster our counter will go. And, Lastly, It would be nice to reset the counter when ever we wanted. This is done using a Latch module, and another Write module. This second Write module uses the other OBC connection on the Read module. There is a priority relationship between the OBC connections that you can read up on in the core manual-For the most part it flows left to right. We can now use a button to clock the 0 out of the Latch and into the Read, thus hard resetting the counter. One note, the inputs should be set to event. The reset button in particular wont work if its set for audio as it will always send out an event.

Final Counter
Final Counter

Next time we’ll make a few improvements, and then use this counter to drive a sin function. Basically, this counter represents the phase component of the sin function. This counter can be used to drive anything and everything you build in Reaktor.

Owen Vallis is one half of Flipmu, and has been working on a series of Reaktor tutorials for exploring intermediate to advanced level digital synthesis. The series looks at such topics as building classic percussion sounds from the Roland-x0x boxes, various ways to approach building a vocoder, sequencers, additive synthesis, and physical modeling. Future tutorials will look at the lower level Reaktor Core, and cover topics such as convolution, auto-correlation, and hopefully some generative systems such as Markov Models and “learning” based macros. 

Flipmu is the home of multi-media artists Owen Vallis and Jordan Hochenbaum. They explore technology, art, sound, and music by building things to interact with.  Previous projects have included the Arduinome, the Chronome, and multi-touch installations using the BrickTable. Both Owen and Jordan teach at the Music Technology: Interaction, Intelligence, and Design program at CalArts.

Cheers,
OhmLab

Have A Question Or Comment About This Tutorial?

Want to ask a question about this tutorial or perhaps you have something to add ?

Click through to our forum post about this tutorial and join the conversation!

Visit: Making Counters in Reaktor Core

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